The present invention relates to three-dimensional stacked microarchitectures and, more particularly, assigning computational tasks on a heterogeneous three-dimensional stacked microarchitecture.
Three-dimensional (3D) stacks are capable of integrating multiple cores and various types of accelerators arranged in a heterogeneous framework. However the increased degree of constraints in 3D creates various challenges when designing and managing 3D stacked architectures. Contrary to 2D architectures, in which optimization targets a single characteristic, 3D stacks are managed with a goal of optimizing multiple characteristics. That is, given the close relationship between performance, power, temperature and reliability characteristics of stacked or 3D architectures it is desirable to avoid optimizing for a single characteristic as in a 2D architecture.
In a 3D stack, run-time management decisions towards improving only a single characteristic are likely to degrade other characteristics. When performing processing tasks, heat is generated within the 3D logic circuit. The heat, if left unchecked, can build and lead to component breakdowns and circuit failures and minimize or even reverse any benefit achieved from performance oriented task assignment decisions. At present there exist thermal management schemes for two-dimensional (2D) circuits. However, 2D thermal management techniques do not address the particular needs of a 3D stacked architecture. As such, during operation, hot spots tend to develop within various layers, and at various points, of the 3D stacks. Overtime, the hot spots will degrade circuit performance and lead to a shorter operational life cycle for the 3D stacked logic circuit.